The present disclosure relates to semiconductors and, more particularly, to structures and methods for forming embedded dynamic random access memory (eDRAM) cells.
Electronic systems typically store data during operation in a memory device. In recent years, the dynamic random access memory (DRAM) has become a popular data storage device for such systems. A DRAM is an integrated circuit that stores data in binary form (e.g., “1” or “0”) in a large number of cells. The data is stored in a cell as a charge on a capacitor located within the cell.
The cells of a conventional DRAM are arranged in an array so that individual cells can be addressed and accessed. Each row of the array includes a word-line that interconnects cells on the row with a common control signal. Similarly, each column of the array includes a bit-line that is coupled to a cell in each row. Thus, the word-lines and bit-lines can be controlled to individually access each cell of the array.
As dynamic random access memory (DRAM) cells are scaled to meet chip-size requirements for future generations, the channel length of transfer devices on the surface of the silicon substrate can no longer be scaled without degrading subthreshold leakage requirements (or retention time requirements). Process steps become complex and incompatible with standard DRAM processes, when vertical transfer devices in the DRAM cell are employed to decouple the channel length from layout ground rules.